#\r
# Compiler options\r
#\r
-CONFIG_COMPILER_OPTIMIZATION_DEFAULT=y\r
-# CONFIG_COMPILER_OPTIMIZATION_SIZE is not set\r
+# CONFIG_COMPILER_OPTIMIZATION_DEFAULT is not set\r
+CONFIG_COMPILER_OPTIMIZATION_SIZE=y\r
# CONFIG_COMPILER_OPTIMIZATION_PERF is not set\r
# CONFIG_COMPILER_OPTIMIZATION_NONE is not set\r
-CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y\r
-# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT is not set\r
+# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE is not set\r
+CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y\r
# CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE is not set\r
CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB=y\r
-CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2\r
+CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=1\r
# CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT is not set\r
CONFIG_COMPILER_HIDE_PATHS_MACROS=y\r
# CONFIG_COMPILER_CXX_EXCEPTIONS is not set\r
# CONFIG_ESP_TLS_CLIENT_SESSION_TICKETS is not set\r
# CONFIG_ESP_TLS_SERVER is not set\r
# CONFIG_ESP_TLS_PSK_VERIFICATION is not set\r
-# CONFIG_ESP_TLS_INSECURE is not set\r
+CONFIG_ESP_TLS_INSECURE=y\r
+CONFIG_ESP_TLS_SKIP_SERVER_CERT_VERIFY=y\r
# end of ESP-TLS\r
\r
#\r
\r
CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE=32\r
CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2304\r
-CONFIG_ESP_MAIN_TASK_STACK_SIZE=3584\r
+CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192\r
CONFIG_ESP_MAIN_TASK_AFFINITY_CPU0=y\r
# CONFIG_ESP_MAIN_TASK_AFFINITY_CPU1 is not set\r
# CONFIG_ESP_MAIN_TASK_AFFINITY_NO_AFFINITY is not set\r
#\r
# Port\r
#\r
-CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y\r
# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set\r
CONFIG_FREERTOS_TLSP_DELETION_CALLBACKS=y\r
# CONFIG_FREERTOS_ENABLE_STATIC_TASK_CLEAN_UP is not set\r
CONFIG_HAL_ASSERTION_EQUALS_SYSTEM=y\r
# CONFIG_HAL_ASSERTION_DISABLE is not set\r
# CONFIG_HAL_ASSERTION_SILENT is not set\r
-# CONFIG_HAL_ASSERTION_ENABLE is not set\r
-CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=2\r
+CONFIG_HAL_DEFAULT_ASSERTION_LEVEL=1\r
CONFIG_HAL_SPI_MASTER_FUNC_IN_IRAM=y\r
CONFIG_HAL_SPI_SLAVE_FUNC_IN_IRAM=y\r
# end of Hardware Abstraction Layer (HAL) and Low Level (LL)\r
#\r
# TLS Key Exchange Methods\r
#\r
-# CONFIG_MBEDTLS_PSK_MODES is not set\r
+CONFIG_MBEDTLS_PSK_MODES=y\r
+CONFIG_MBEDTLS_KEY_EXCHANGE_PSK=y\r
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK=y\r
+CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK=y\r
CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y\r
CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y\r
CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y\r
# CONFIG_SPI_FLASH_VERIFY_WRITE is not set\r
# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set\r
CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y\r
-CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS=y\r
+# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ABORTS is not set\r
# CONFIG_SPI_FLASH_DANGEROUS_WRITE_FAILS is not set\r
-# CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED is not set\r
+CONFIG_SPI_FLASH_DANGEROUS_WRITE_ALLOWED=y\r
# CONFIG_SPI_FLASH_SHARE_SPI1_BUS is not set\r
# CONFIG_SPI_FLASH_BYPASS_BLOCK_ERASE is not set\r
CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y\r
CONFIG_FLASHMODE_DIO=y\r
# CONFIG_FLASHMODE_DOUT is not set\r
CONFIG_MONITOR_BAUD=115200\r
-CONFIG_OPTIMIZATION_LEVEL_DEBUG=y\r
-CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG=y\r
-# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set\r
-# CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE is not set\r
-CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y\r
-# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set\r
+# CONFIG_OPTIMIZATION_LEVEL_DEBUG is not set\r
+# CONFIG_COMPILER_OPTIMIZATION_LEVEL_DEBUG is not set\r
+CONFIG_OPTIMIZATION_LEVEL_RELEASE=y\r
+CONFIG_COMPILER_OPTIMIZATION_LEVEL_RELEASE=y\r
+# CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED is not set\r
+CONFIG_OPTIMIZATION_ASSERTIONS_SILENT=y\r
# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set\r
-CONFIG_OPTIMIZATION_ASSERTION_LEVEL=2\r
+CONFIG_OPTIMIZATION_ASSERTION_LEVEL=1\r
# CONFIG_CXX_EXCEPTIONS is not set\r
CONFIG_STACK_CHECK_NONE=y\r
# CONFIG_STACK_CHECK_NORM is not set\r
# CONFIG_ESP32_PANIC_GDBSTUB is not set\r
CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32\r
CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304\r
-CONFIG_MAIN_TASK_STACK_SIZE=3584\r
+CONFIG_MAIN_TASK_STACK_SIZE=8192\r
CONFIG_CONSOLE_UART_DEFAULT=y\r
# CONFIG_CONSOLE_UART_CUSTOM is not set\r
# CONFIG_CONSOLE_UART_NONE is not set\r
# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set\r
CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1\r
CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread"\r
-CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y\r
+# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS is not set\r
# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set\r
-# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set\r
+CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED=y\r
# CONFIG_ESP32_ULP_COPROC_ENABLED is not set\r
CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y\r
CONFIG_SUPPORT_TERMIOS=y\r